As a rule of thumb for designing this classical biasing circuit, we choose $R_D$ and $R_S$ to provide one-third of the power-supply voltage $V_{D D}$ as a drop across each of $R_D$, the transistor (i.e., $V_{D S}$ ) and $R_S$. For $V_{D D}=15 \mathrm{~V}$, this choice makes $V_D=+10 \mathrm{~V}$ and $V_S=+5 \mathrm{~V}$. Now, since $I_D$ is required to be 0.5 mA , we can find the values of $R_D$ and $R_S$ as lollows:

$$
\begin{aligned}
& R_D=\frac{V_{D D}-V_D}{I_D}=\frac{15-10}{0.5}=10 \mathrm{~kJ} 2 \\
& R_S=\frac{V_S}{R_S}=\frac{5}{0.5}=10 \mathrm{kS} 2
\end{aligned}
$$


The required value of $V_{G S}$ can be determined by first calculating the overdrive voltage $V_{O V}$ from

$$
\begin{aligned}
I_D & =\frac{1}{2} k_n^{\prime}(W / L) V_{O V}^2 \\
0.5 & =\frac{1}{2} \times 1 \times V_{O V}^2
\end{aligned}
$$

which yields $V_{O V}=1 \mathrm{~V}$, and thus,

$$
V_{G S}=V_{\mathrm{r}}+V_{O V}=1+1=2 \mathrm{~V}
$$


Now, since $V_S=+5 \mathrm{~V}, V_C$ must he

$$
V_G=V_S+V_{G S}=5+2=7 \mathrm{~V}
$$


To establish this voltage at the gate we may select $R_{G 1}=8 \mathrm{M} \Omega$ and $R_{G 2}=7 \mathrm{M} \Omega$. The final circuit is shown in Fig. 4.31. Observe that the dc voltage at the drain ( +10 V ) allows for a positive sigual swing of +5 V (i.e., up to $V_{D D}$ ) and a negative signal swing of -4 V [i.e., down to $\left.\left(V_G-V_i\right)\right]$.

If the NMOS transistor is replaced with another having $V_t=1.5 \mathrm{~V}$, the new value of $I_D$ can be found as follows:

$$
\begin{aligned}
I_D & =\frac{1}{2} \times 1 \times\left(V_{G S}-1.5\right)^2 \\
V_G & =V_{G S}+I_D R_S \\
7 & =V_{G S}+10 I_D
\end{aligned}
$$

$$
I_D=0.455 \mathrm{~mA}
$$


Thus the change in $I_D$ is

$$
\Delta A_D=0.455-0.5=-0.045 \mathrm{~mA}
$$

which is $\frac{-0.045}{0.5} \times 100=-9 \%$ change.